Field Effect Transistors

Article : Andy Collinson
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Introduction
The Junction Field Effect Transistor JFET (or FET for short) is a three terminal, gate, source and drain device available in n-channel and p-channel types, symbols shown left and right.

In this article, I am using LTspice to simulate the FET's device characteristics. The FET is a voltage controlled device and has a very high input impedance. A smaller input voltage controls a larger output current. This property is called transconductance. In some applications JFET's have been replaced by the MOSFET.




Device Characteristic Curves
In JFET's the gate is insulated from the substrate by being reverse-biased. The bias is negative with respect to the source causing a depletion region to form between the gate and the substrate. The FET can be used in common source, common gate or common drain (also known as source follower) mode. Each configuration has slightly different characteristics.

Common Source Output Characteristic Curves

To produce the common source characteristic curves the circuit was setup as shown in Figure 1. Using LTspice a DC sweep was performed. The drain voltage was swept from 0 to 20 Volts for values of gate source voltage over -3V to 0V in 0.5V steps.

The gate-source supply VGS biases the gate terminal negative with respect to the source. An N-channel 2N2819 was used, the circuit can be downloaded here.



The Plot of Drain-Source Voltage versus drain current for the 2N2819 is shown below:

The top curve is for a gate-source voltage VGS of 0V and successive curves have a gate-source reduced by 0.5V increments. The lowest trace (red) is for VGS = -3V.

Pinch-Off Voltage
As can be seen in the above graph, at a certain reverse bias voltage, no drain current will flow at all, this is called the "pinch-off" voltage. The "pinch-off voltage"(Vp) varies considerably, even among devices of the same type. The pinch-off voltage for an n-channel device requires a negative gate-source voltage (), conversely, to switch off a p-channel device requires a positive VGS.


Output Resistance
The slope of the output characteristic curves, ΔVDS / ΔId will give the output resistance of a FET. As drain currents are usually small, the output resistance is high and the output impedance of the stage is set by the drain resistor.



Common Source Input Characteristic Curves

To produce the common source input characteristic curves the circuit was setup as shown in Figure 2. Using LTspice a DC sweep was performed. The drain voltage was fixed at 20 Volts and the gate source voltage swept over the range -3V to 0V in 0.5V steps.


FET Transconductance
As mentioned in the introduction, a smaller input voltage controls the FET's output current. This property is called transconductance. Transconductance is measured in mA/V and given the symbol gm. Transconductance is generally measured in Siemens, although sometimes you will see the alternative unit mho.
gm = Δ Iout
Δ Vin
From the slope of the input characteristics, you can measure the change in input voltage, against change in drain current. The two vertical white lines are cursors and the values shown below.

As shown above, a change in gate-source voltage from -1.8V to -1.2V gives rise to a change in drain current from 1.9mA to 4.4mA The difference box already calculates the change as 0.00407 Siemens. This is just over 4mS for the 2N3819.

As the input characteristic is not a straight line, then the transconductance will vary, with gate-source voltage and collector current. These changes must be allowed for in any design. Transconductance also varies between devices.


Self-Biased JFET Amplifier
To make a common drain amplifier, all you need are three resistors. The gate resistor, holds the JFET gate potential at 0V, and sets the input resistance. The source resistor is used to bias the source terminal. The drain resistor is used to set the voltage gain, the circuit drawn in LTSpice is below:
DC Operating Point
Now that we have the characteristic I-V plot for the device, we must chose a DC operating point for the device. This point is commonly called the Q point (quiescent point). This point is arbitrary, and a circuit can be developed to bias the JFET to operate at this point; however, there are some factors to consider when picking the Q point for your circuit.

To minimize signal distortions, an amplifier needs to work in the linear region of the output characteristic curves. For a JFET the optimum point is in the constant current region. In addition, for maximum signal output, the JFET needs to be biased so that the the drain-source voltage is halfway between the supply voltage and the pinchoff voltage.

To minimize power consumption a low value of drain current is chosen, just sufficient to produce an unclipped output waveform to the load. In this example I will use a Q point with a drain current of approximately 5 mA and a drain-source voltage of approximately 11 V.

Once the Q point has been decided, the only other requirement is supply voltage. For maximum output swing the supply voltage is usually about double the Q point and will be set at 20V.

The next stage is construction of the DC load line. The load line starts on the X axis at maximum supply voltage and is a straight line, through the Q point, to the Y axis. In LTspice a load line can be created by right clicking the simulation, then add line. As shown below a vertical line can be drawn on the X axis at the bias point of 11V. Then a new line with arrow is drawn, the first point starts on X axis at 20V, the second point now intersects with the bias line at 11V and the Y axis drain current of 5mA. This line is now the DC load line, which the circuit will always operate along. Annotations can be made by pressing "t" in LTspice. The load line is shown below.

Figure 3 - DC Load Line for Amplifier

Now that the load line is complete the resistor values can be calculated. The slope of the load line determines the total resistance of the drain and source resistors. This resistance is determined by the X intercept (20V) divided by the point where the load line crosses the Y axis. Zooming in this value is about 11.9mA. The total resistance is 20V / 11.9mA = 1680 ohms.

From Figure 3 the q point crosses the line at Vgs = -1V and source current = 5.324mA, To bias the gate to the required voltage, a source resistor (Rs) is required. As Vgs = -IdRs then Rs = -1V/-(5.324 mA) = 188 ohms

As total resistance is 1680 ohms and a source resistor of 188 ohms was calculated, the remaining 1492 ohms will be used as the drain resistor. A gate resistor Rg of 1Meg will be used.

The operating point of the circuit can be verified by running a SPICE simulation. As you can see from Figure 3, the drain current is 5.32 mA, and the drain-source voltage is 12.065 -1 = 11.065V. These values are almost identical to the Q point on the load line shown in Figure 3.


Figure 4 - SPICE Simulation of Circuit

Transient Analysis (Time Domain)

Now that the single stage has been designed we can simulate how it will perform in the time domain. This is very similar to viewing the waveform on an oscilloscope. In LTspice the transient command is used (.tran). Before we view the simulation a signal generator and input dc blocking capacitor must be added to the circuit. The signal generator will be set to 1kHz and a peak amplitude of 100mV will be used. Note that the peak to peak value is double the peak value. As 1KHz is used, the time taken for 1 cycle is the reciprocle of the input frequency or 1/1k = 1ms. You will always need to know this before hand and can therefore set the stop time for the transient simulation command. Some circuits require a finite time to stabilize so it its always a good idea to view at least 3 complete output cycles, The stop time will therefore be set to 3ms.


Figure 5 - Transient Simulation

Figure 5 above left shows the modified circuit with signal generator, while the right hand side shows the output waveform after 3 cycles. The command is .tran 0 3m where 0 represents the start time and stop time is 3ms. The output waveform is taken from the drain and therefore has a standing DC offset of 12.065V. A practical circuit would require an output decoupling capacitor and load resistor to remove this offset voltage.

Harmonic Distortion (Fourier Analysis)

Because the output characteristic curves shown in Figure 3 are a curve and not linear, some signal distortion will occur. To minimize distortion the circuit is biased so that the Q point is approximately in the middle of the horizontal curve. This also allows for maximum and minimum output swing.Total harmonic distortion (THD) refers to a device adding harmonics that were not in the original signal. This happens due to non-linearities in the output curve, incorrect biasing and excessive input signal. The THD is the square root of the sum of the squares of the individual harmonic amplitudes. In LTspice the Fourier command is called .four followed by the fundamental frequency, and then the output voltage node or label where the THD is calculated. As the signal generator is set to 1KHz this is the fundamental and an output node called Vout is added to the schematic in Figure 5. The Fourier command is: .four 1KHz V(Vout)

Once the circuit has been simulated, the fourier analysis is performed on the transient waveform and results from LTspice are available by pressing ctrl+L or, alternatively from the View Menu under Spice ErrorLog. Results below:

Fourier components of V(vout)
DC component:12.0646

Harmonic	Frequency	 Fourier 	Normalized	 Phase  	Normalized
 Number 	  [Hz]   	Component	 Component	[degree]	Phase [deg]
    1   	1.000e+03	3.923e-01	1.000e+00	 -179.91°	    0.00°
    2   	2.000e+03	1.093e-03	2.787e-03	   95.14°	  275.05°
    3   	3.000e+03	1.780e-04	4.538e-04	 -178.51°	    1.40°
    4   	4.000e+03	1.806e-04	4.603e-04	   30.48°	  210.39°
    5   	5.000e+03	1.523e-04	3.881e-04	  -16.54°	  163.37°
    6   	6.000e+03	1.066e-04	2.718e-04	 -160.93°	   18.98°
    7   	7.000e+03	1.783e-04	4.545e-04	  166.42°	  346.33°
    8   	8.000e+03	1.606e-04	4.093e-04	 -127.52°	   52.39°
    9   	9.000e+03	1.141e-04	2.907e-04	   51.79°	  231.70°
Total Harmonic Distortion: 0.297813%(0.306689%)

The first line shows the node or label where the Fourier analysis was calculated and the second line shows the DC component. The next lines calculate nine harmonics starting at 1kHz up to 9kHz. Scientific notation is used as some of the fourier components can be quite small. The last line is the sum of the 9 harmonics and gives the overall THD as 0.29% with 0.1V input.

Overload and distortion
What happens when the input signal is too high? With excessive input signal, the output signal would try to move outside the limits of the load line, and as the output signal reaches the limits of the supply voltage or pinchoff region there would be distortion on each half of the waveform. If the signal generator Vin is increased to 3V peak to peak amplitude and the circuit re-run the THD increases to 14.4% as seen below:

Fourier components of V(vout)
DC component:12.4545

Harmonic	Frequency	 Fourier 	Normalized	 	Phase  	Normalized
 Number 	  [Hz]   	Component	 Component	[degree]	Phase [deg]
    1   	1.000e+03	9.243e+00	1.000e+00	 	-179.79	    0.00
    2   	2.000e+03	8.700e-01	9.413e-02	  	  91.15	  270.93
    3   	3.000e+03	9.661e-01	1.045e-01	 	-179.60	    0.19
    4   	4.000e+03	2.271e-01	2.457e-02	  	 92.54	  272.33
    5   	5.000e+03	1.643e-01	1.778e-02	   	1.68	  	181.46
    6   	6.000e+03	2.551e-02	2.760e-03	  	 -93.08	   86.71
    7   	7.000e+03	5.989e-02	6.480e-03	      1.72	  	181.50
    8   	8.000e+03	4.967e-02	5.374e-03	  	 -89.00	   90.79
    9   	9.000e+03	5.305e-02	5.740e-03		-176.55	    3.23
Total Harmonic Distortion: 14.428836%(14.436002%)

References:
Analyzing Circuits with SPICE on Linux

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